1. Field of the Invention
This invention is related to the field of processors and, more particular, to instructions which cause processor state to be saved to memory in processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes. Thus, it may be desirable to provide an architecture which is compatible with the x86 processor architecture but which includes support for 64 bit processing as well.
Unfortunately, extending the x86 processor architecture to 64 bits may be problematic. For example, the x86 processor architecture specifies a segmented memory space in which variable sized memory segments may be allocated to store code (instructions) and data. Segment tables in memory store information identifying the segments, including a base address which is 32 bits in the x86 processor architecture. Extending the base address to address sizes larger than 32 bits (e.g. 64 bits) would require redefining the segment tables and may create compatibility issues. Furthermore, the x86 processor architecture specifies state save and state restore instructions (e.g. FXSAVE and FXRSTOR) which save various register state to a block of memory, including at least two memory pointers (the instruction pointer of the most recent floating point instruction and the data pointer to the most recent floating point memory operand). These pointers are segmented pointers, including a segment selector identifying the segment and a logical address within that segment. Extending the operation of these state save and state restore instructions to larger address sizes would be required.
A processor is described which supports at least two different state save formats. Each format stores state in the form that the state exists in one or more operating modes of the processor. The operand size of the state save and state restore instructions may be used to indicate which state format is assumed by the processor during execution of the state save and state restore instructions. Thus, multiple formats may be supported. If the state save and state restore instructions are executed in the operating system, for example, which may execute in the same operating mode even though various other code sequences may be executed in a variety of operating modes, the appropriate format may be used by encoding the state save and state restore instructions with the appropriate operand size.
In one implementation, the processor implements a processor architecture compatible with the x86 architecture with enhancements to support 64 bit addressing and processing. In modes in which 64 bit addressing is supported, segmentation is not used. Thus, the segment base addresses need not be extended beyond 32 bits for code and data segments. In 32 bit and 16 bit modes, segmentation is used. Thus, the address of a floating point instruction may be indicated by a segment selector Of and pointer or by a pointer only, depending on the operating mode active during execution of the floating point instruction. Similarly, the address of a floating point memory operand may be indicated by a segment selector and pointer or by a pointer only. Thus, the operand size of the FXSAVE/FXRSTOR instruction may be used to distinguish which type of information is stored and retrieved.
Broadly speaking, a processor is contemplated comprising a plurality of registers and an execution core coupled thereto. The execution core, responsive to a first instruction, is configured to store a state of the plurality of registers to a memory region specified by the first instruction. The plurality of registers include one or more registers storing a floating point instruction pointer and a code segment selector, and wherein the execution core, responsive to an operand size of the first instruction being a first operand size, is configured to store the floating point instruction pointer and the code segment selector in a first storage location of the memory region. Responsive to the operand size of the first instruction being a second operand size, the execution core is configured to store only the floating point instruction pointer in the first storage location.
Additionally, an apparatus is contemplated comprising a plurality of storage locations corresponding to a plurality of registers and a processor coupled thereto. The processor, responsive to a first instruction, is configured to store a state of the plurality of registers to a memory region specified by the first instruction. The plurality of registers include one or more registers storing a floating point instruction pointer and a code segment selector, and wherein the processor, responsive to an operand size of the first instruction being a first operand size, is configured to store the floating point instruction pointer and the code segment selector in a first storage location of the memory region. Responsive to the operand size of the first instruction being a second operand size, the processor is configured to store only the floating point instruction pointer in the first storage location.
Moreover, a method is contemplated. A first instruction is executed, the first instruction having an operand size. A state of a plurality of registers is stored in a memory region specified by the first instruction. The plurality of registers include one or more registers storing a floating point instruction pointer and a code segment selector. The storing comprises: (a) storing, responsive to an operand size of the first instruction being a first operand size, the floating point instruction pointer and the code segment selector in a first storage location of the memory region; and (b) storing, responsive to the operand size of the first instruction being a second operand size, only the floating point instruction pointer in the first storage location.